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The nVIDIA nForce Motherboard Chipset:
a different perspective

Last updated: 6/28/01

nVIDIA nForce Chipset - Integrated Graphics Processor (IGP)Here are feature highlights of each chip:

The IGP consists of about 20 million transistors that are organized into three principle units:

Twin Bank Memory Architecture, which is implemented through dual-independent, 64-bit memory controllers.  It provides a 266 MHz, 128-bit wide access path to Double Data Rate (DDR) memory.  The result is a 4.2 GBytes/sec. peak memory bandwidth.   This compares to 2.1 GBytes/sec. for other DDR chipsets.  Towards the high end of the PC graphics performance spectrum, the nVIDIA’s GeForce3 display adapter has four 64-bit memory controllers and a 256-bit access path to its on board DDR memory.

Dynamic Adaptive Speculative Pre-processor (DASP).   The DASP uses intelligent, pre-processing technology to exploit unused memory bandwidth to load its cache (1024 bytes) with application instructions and data the CPU is expected to request later.  When the CPU requests the data, it is returned to the CPU immediately rather waiting for it to be accessed from memory.  Translation: the DASP is a smart memory cache’ system.

Graphics Processor Unit (GPU).   The GPU uses GeForce2 MX core.  With the Twin Bank Memory Architecture it is capable of a maximum graphics throughput of 350 megapixels/sec. and does not have the stellar imaging performance of the sup’d-up GeForce3 GPU in the Xbox, but it is certainly faster than many run-of-the-mill display adapters and the graphics cores currently integrated into other Northbridge chips.  The GPU does use system memory for its frame buffer (32 Mbytes) and shares memory bandwidth with the rest of the system like other chipsets and motherboards with built-in graphics, but this is mitigated by Twin Bank Architecture’s 128-bit memory pipe, the use of DDR system memory, and the current, price-driven transition of mainstream PC’s from 128 to 256 MBytes of memory.  Also, because of the integration of the GPU with other units in the MCP, complex graphics calculations can be performed directly in the GPU itself without having to communicate back and forth across the AGP bus with the CPU.  This frees-up the CPU for other tasks.

The IGP has an external 4X/8X AGP bus to accommodate higher-performance, plug-in display adapters.  It also has a TV encoder interface which multiplexes on the external AGP bus, supports HDTV resolutions, and supports simultaneous TV and monitor displays.

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